In the field of programmable logic devices, it is typical for an engineer designing logic for a particular application to provide, from a variety of available discrete logic components, a logic configuration capable of performing the required input translation from an output of a first logic device to an input of a second logic device. This translation function is necessary due to the variety of circuit applications which may require, among other things, either a high true or low true logic. Thus, in a situation where a plurality of outputs are provided from logic circuits, some of which include high true logic and some of which include low true logic, it has previously been necessary to design particular circuitry directed to translating all of the outputs to a single logic condition. Use of discrete logic components, however, has the disadvantage of slow speeds in the circuit's operation.
For instance, in a situation where six inputs are provided to a logic circuit, three of which inputs come from devices having high true logic and three of which inputs come from devices having low true logic, a design engineer may have initially selected an eight input NAND device such as a 7430 and utilized a 7404 hex inverter to implement the circuit arrangement. Since most of the propagation delay in an integrated circuit is incurred upon the entering and leaving of a chip, this approach requires three traverses of integrated circuits, and thus, includes a three-chip delay. Additionally, two logic devices are required in order to accomplish this relatively simple translation of the six inputs such that they can all be provided to a high true logic device.
Due to the complexity of designing some translation portions of a circuit from discrete components, design engineers have migrated to the use of complex programmable logic arrays (PLA). However, use of these complex arrays require substantial area on an integrated chip resulting in large power consumption and slower speeds of operation. These losses become even more pertinent when much of the array is not required by the specific application, thereby making use of these complex arrays inefficient, wasteful and costly.
Another disadvantageous feature of these programmable logic arrays is the incorporation of a programmable fuse in the AC path of the circuit. If the fuse is left intact such that the respective line is included in the array, the speed of the circuit's operation is further reduced by the presence of the fuse in the AC path.
It is, therefore, an object of the present invention to provide a new and improved programmable logic device.
It is another object of the present invention to provide a new and improved programmable circuit which is adapted for implementation on a single integrated circuit.
It is still another object of the present invention to provide a new and improved programmable integrated circuit which selectively provides an active low or active high for each input and output of the circuit.
It is a further object of the present invention to provide a new and improved integrated circuit which performs the programmed logic functions utilizing minimal space without wasting area unnecessarily for simple applications of logic.
It is further an object of the present invention to provide a new and improved integrated circuit which performs the programmed logic functions at an improved speed.
It is still further an object of the present invention to provide a new and improved integrated circuit which performs the programmed logic function using low power.
It is another object of the present invention to provide a new and improved programmable integrated circuit which eliminates the use of fuses or their equivalent in the logic AC path of the logic components.
In accordance with the invention, an input macro cell comprising a programmable logic circuit selectively controls input circuits to which the logic circuit is to be responsive as well as the polarity of the input circuit, such that when a selected pattern of input signals are received, an output signal is provided of a controllable polarity.
In accordance with another feature of the invention, a programmable means for controlling the polarity of the output signal to provide either a low true logic or a high true logic output signal.
A further feature of the invention is to combine in parallel a plurality of the above-mentioned input macro cell circuits and provide the respective outputs to an additional output macro cell comprising a programmable logic circuit which can selectively control which signals it is to receive from the respective input macro cells. Additionally, the output programmable logic circuit is programmable such that its output may be selectively inverted to accommodate high true or low true logic.
In a specific embodiment of the invention, an input macro cell (IMC) is provided which includes a multiple input AND gate. Coupled to each input of the AND gate are programmable OR gates which by way of blowing fuses at respective inputs of the OR gates can vary the width of the AND gate to a specific application. An exclusive OR gate is provided to an input of each each OR gate which by way of blowing fuses at respective inputs of the exclusive OR gates, provides for selectively programming the polarity of the logic signal each exclusive OR gate is to receive. Thus, each input to the multiple AND gate can be selectively inhibited as well as made low true logic or high true logic. Additionally, an exclusive OR gate may be provided at the output of the AND gate such that by way of a fuse, the output can be selectively programmed to be a low true or high true logic.
The invention, therefore, provides a programmable logic circuit which can be programmed to implement AND, OR, NAND, NOR, or inverting logic functions. This is accomplished by selectively programming the polarities of both the inputs and output. As noted above, the logical results of several IMC's can be used as inputs to an output macro cell (OMC) for the purpose of either increasing the number of variables on a given output function, thereby widening the gate or increasing the number of overall logic levels replaced.
In accordance with another embodiment of the invention, an OMC is provided which includes a multiple input NOR gate. At each input of the NOR gate is an equivalent to a NOR gate with a fuse incorporated in an input of each NOR gate. By way of blowing selected fuses, the width of the OMC can be varied, deselecting those inputs not required for the specific application. An exclusive OR gate is provided at the output of the multiple input NOR gate which by way of a fuse can be selectively programmed to provide a low true or high true logic output signal. As a result of combining a plurality of IMC's in combination with one or more OMC's, complex structures such as AND-OR-INVERT, can be realized. Because of the integrated nature of the above circuits, however, the loss of speed as with discrete logic components or the loss of power and area on die of the more complex programmable logic circuits are avoided.
Further objects, features, and advantages of the present invention will become more apparent from the following description when taken with the accompanying drawings which show, for purposes of illustration only, an embodiment in accordance with the present invention.